日本と海外をつなぐクラウドソーシング

Acronics System, Inc

PCB Layout Trainee

2008/08～ 2008/12

Training on Cadence Allegro PCB Design Tool

DCSELAB

Laboratory Research Student

2012/06～ 2012/10

Design and implement Viterbi decoder core (VHDL) adapting IEEE STD 802.16-2009 standard on Altera DE2 Board. Build testing environment for verifying and BER evaluating the design.

eSilicon

Memory IP Circuit Design Engineer

2014/05～ 2015/07

Do characterization and QCs for design
- Characterize timing/power on specific process for all PVTs, all defined instances.
- Complete curve-fitting: do regression and generate synlib and datasheet for trend check and min-constraint check, and validate PPA comparison data.
- Complete timing/power trend check and min-constraint check (on defined instances) on LPE , timing/power comparison (critical path and full instance on defined instances) to insure the timing/power data in synlib and datasheet are valid.
Do QA for design: validate data package.
- Complete EDA views check to insure the correctness of FE views & BE views in term of data compatibility, consistency.
- Complete all general checks (timing/power trendcheck, data presentation, name collision, release notes, package’s tag/version, eMC,…)